Intel’s first large and small core architecture is released, and the book data looks pretty good

After all the calls came out, Intel’s first performance hybrid architecture, code-named Alder Lake, can also be regarded as the first time that the twelfth-generation Core has finally come out.

Although the large and small core architectures are very common on mobile phone processors, this is the first time on Intel’s desktop. With the announcement of the technology roadmap earlier, plus the new content of this architecture day, I have to say that Intel is now The pace is fast.

Raja Koduri, Intel’s senior vice president and general manager of the Accelerated Computing System and Graphics Division, said bluntly:

Architecture is the alchemy of hardware and software.

So what the new core architecture looks like is closely related to what kind of equipment we use later. Similar to mobile phone processors, Alder Lake also classifies large and small cores into performance cores and energy efficiency cores. The former is responsible for high-performance and high-load tasks, and the latter is dedicated to completing low-load tasks.

Intel’s new performance core microarchitecture, once code-named Golden Cove, aims to increase speed and break through the limitations of low latency and single-threaded application performance. The code size of workloads is constantly growing, and stronger execution capabilities are required. The data set has also increased substantially as the demand for data bandwidth increases. Intel's new performance core microarchitecture has brought significant growth rates while better supporting applications with larger code volumes.

The performance core has a wider, deeper, and smarter architecture:

  • Wider: Decoder increased from 4 to 6, 6µop buffer increased to 8µop, allocation increased from 5 to 6 channels, execution ports increased from 10 to 12
  • Deeper: larger physical register files, with a reordering buffer of 512 entries
  • Smarter: Improved branch prediction accuracy, reduced effective first-level delay, and optimized second-level full write prediction bandwidth

The performance core is the highest performance CPU core Intel has ever built. It breaks the limits of low latency and single-threaded application performance through the following features: Compared with the current 11th generation Core processor architecture (Cypress Cove), it is At the ISO frequency of performance, an average improvement of about 19% was achieved for a wide range of workloads.

The new Intel energy-efficient core microarchitecture, once code-named Gracemont, is designed to face today's multitasking scenarios, improve throughput efficiency and provide scalable multithreading performance. This energy-efficient x86 micro-architecture realizes multi-core task load in a limited silicon chip space and has a wide frequency range. The architecture is committed to reducing overall power consumption through low-voltage energy efficiency cores, and providing power and thermal space for higher frequency operation. This also allows energy efficiency cores to improve performance to meet more dynamic task loads.

Energy efficiency cores can take advantage of various technological advances to prioritize workloads without consuming processor power, and directly improve performance through the number of instructions per cycle (IPC) improvement function. These functions include:

  • Branch target cache with 5000 entries for more accurate branch prediction
  • 64KB instruction cache, save available instructions without consuming the power of the memory subsystem
  • Intel’s first on-demand instruction length decoder that can generate pre-decoded information
  • Intel's cluster out-of-order execution decoder can decode up to 6 instructions per cycle while maintaining energy efficiency
  • Wide Back End has 5 sets of five-wide allocation and 8 sets of width retirement, 256 out-of-order window entries and 17 execution ports
  • Support Intel Control Flow Enforcement Technology and Intel Virtualization Technology Redirection Protection and other functions
  • Realizes the AVX instruction set and new extensions that support integer artificial intelligence operations

Compared with Intel’s most prolific CPU core Skylake, under single-threaded performance, energy-efficient cores can achieve a 40% performance improvement under the same power consumption, or provide the same performance when the power consumption is less than 40%. Compared with two Skylake cores running four threads, the throughput performance provided by four energy-efficient cores can simultaneously bring 80% performance improvement under the condition of lower power consumption, and when providing the same throughput performance , The power consumption is reduced by 80%.

It can be seen that in terms of book data, Alder Lake is very worth looking forward to. Whether it is power consumption or performance, it can be called a good-performing generation.

Alder Lake is based on Intel 7 process technology and supports the latest memory and fastest I/O.

Prior to this, Intel stated that it will no longer adopt the node naming rules that were previously common in the industry and based on nano-process technology, but will adopt a brand-new naming scheme.

Intel 7: The third-generation 10nm chip is renamed to Intel 7 (replacing last year’s enhanced SuperFin), which will provide 10-15% performance per watt. It has been put into mass production and will bring Alder Lake consumer-grade processors and Sapphire Rapids data Central processor.

Intel 4: The 7nm node is renamed to Intel 4. Compared to Intel 7, the performance per watt is increased by 20%. EUV lithography technology will be used. The first application products are Meteor Lake and Granite Rapids. Meteor Lake will use Foveros packaging technology to support a TDP range of 5 to 125W, and is expected to be launched at the end of 2022.

Intel 3: The Intel 3 node is expected to be unveiled in the second half of 2023. It is expected to be an upgraded application of the Intel 4 7nm process. Compared with Intel 4, the performance per watt is improved by about 18%. Although it is not stated clearly, it is expected that it will not be marketed until 2024 at the earliest.

In short, the 10nm ESF was renamed Intel 7, the 7nm was renamed Intel 4, and the 7nm enhanced version was renamed Intel 3.

According to Intel, Alder Lake supports all client devices from ultra-portable notebooks to enthusiasts to commercial desktops. It uses a single, highly scalable SoC architecture and provides three types of product design forms:

  • High-performance, dual-chip, socket-type desktop processor with leading performance and energy efficiency. Support high specification memory and I/O
  • High-performance notebook processor, using BGA package, and adding image unit, larger Xe graphics card and Thunderbolt 4 connection
  • Thin, low-power notebook processor, using high-density packaging, configuration optimized I/O and power transmission

In the plastic greenhouse of destiny, every cabbage that has been sprayed with too much pesticide once had a dream of becoming a pollution-free organic vegetable.

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