Apple wants to take “King Fried Chips” to visit Jurassic Park | Hard Philosophy

There are still many puzzles about Apple's self-developed chip M1 series.

Just recently, there have been many rumors about the follow-up of the M1 chip, M2 and M3, but most of them are information that catches the eye. There is no clear information about the architecture, performance, and core, but more about TSMC. Upgrade of process nodes.

▲ M1 hasn't finished yet, M2 and M3 may be coming soon. Picture from: progamer

TSMC's 4nm, 3nm and other new process technologies may be larger upgrade points. In this way, in the M1 series that has already amazing the energy consumption ratio, M2 and M3 only increase.

But, after two years, when the node process is upgraded to 3nm?

There are about two, one is to dry the node process to 1nm, wirelessly approaching the physical limit, but it is more difficult. The other is to bypass the benefits of node process upgrades and take the path of Chiplet's "small chips".

Is an M1 Max not enough? Then install two Mac Pro

However, Apple, which has always disliked being at the mercy of the supply chain, may be looking for a feasible way while taking advantage of the high energy efficiency ratio of nodes and ARM chips.

From M1 to the more powerful M1 Pro and M1 Max, they have almost the same architecture. The performance release of single core is relatively close. The biggest difference is actually the number of cores.

Even, you can simply understand that ARM-based M chips rely on the number of heap cores to obtain a higher performance ceiling.

  • M1: CPU 4+4 cores, GPU 8 cores, 16 billion transistors, 16 core neural network;
  • M1 Pro: CPU 2+8 cores, GPU 16 cores, 33.7 billion transistors, 16 core neural network;
  • M1 Max: CPU 2+8 cores, GPU 32 cores; 57 billion transistors, 16 core neural network;

Simply looking at it from another dimension, the chip area of ​​M1 is about 120mm² and that of M1 Pro is 245mm². When it comes to M1 Max, it soars directly to M1 Max 432mm².

For the same generation of M chips, the more Max, the more the core number and chip area are. From here, it is not difficult to understand Apple's naming rules for M chips. It is easy to understand. Microsoft, Intel, and Qualcomm should really study hard.

Although Tim Millet, Apple’s chip architect and vice president, explained in detail on the Upgrade podcast in November, Apple’s hard-working journey in developing the M chip, but for the next development of the M chip, and How to change Max on the basis of Max has not mentioned a word.

▲ Apple chip architect and vice president Tim Millet (Tim Millet). Picture from: Apple

With the MacBook Pro 14/16 on the market one after another, after many private DIYer exploration, it seems that Apple has also made the M1 Max more Max foreshadowing.

That is "Put two M1 Max in, and you can even double it."

▲ M1 Max hidden area. Picture from: HothardWare

This conjecture is actually based on the disassembly and found that the M1 Max has an extra "unknown area" compared to the M1 Pro. After some brainstorming, it is guessed that it is a "high-speed bus" reserved for connecting two or more M1 Max.

▲ Tim Cook: Intel, this is for you. Picture from: Max Tech

This also fits the rumors that the new iMac Pro and Mac Pro will use multiple M1 Max processors. "It's like playing Lego, piling up wood, and hitting the master indiscriminately."

However, the term "pile of wood" is not very accurate, and "puzzle" is more accurate. In this way, the chip area of ​​the double M1 Max will be quite considerable, and four times that is unprecedented.

M1 Max Duo surpasses Nvidia's top GPU GA100. The chip area (826mm²) is almost certain.

Such a huge SoC, looking at the entire semiconductor history, can definitely be counted as a "Tyrannosaurus"-level chip, not to mention that it will be based on a 5nm process, and the cost is very likely to exceed any contemporary chip.

When M series chips enter "Jurassic Park"

From the original computer ENIAC weighing 30 tons and covering an area of ​​170 square meters, to the current desktop PC, almost all equipment is developing towards miniaturization and integration.

The same is true for processors in the semiconductor world. When the process node is still μm, the area of ​​Intel's first Pentium (Pentium) is about 294mm², based on the 0.8μm process.

▲ Intel Pentium III Xeon.

In the x86 processor era, Intel Pentium III Xeon has an area of ​​385mm² and is based on a 0.18μm process. However, at that time, many processor manufacturers were strictly controlling the volume and suppressing the cost and introduced relatively affordable PCs to promote them to the general public.

In the future, whether it is the popularity of 64-bit or the leap of process nodes, the size of the processor is mostly controlled below 500mm². Under the premise of cost control and efficient use of wafers, it has almost stopped the consumer-grade processor from facing the "dinosaurization". "development of.

The consumer semiconductor industry seems to have gradually moved from the Jurassic to a new era.

▲ Folk gods are also making suggestions for the development of Apple's M chip. Image from: Twitter

At this time, the possible development route of Apple's M chip seems to have rewinded to the "Jurassic", but while the size of the processor has advanced, the density of transistors has not fallen.

Although it sounds like it shouldn't be difficult to put two chips together, and there is no need to redesign the architecture and core. But in reality, with the increase of chip area (especially the doubled growth) and the guarantee of sufficient yield and production capacity, the cost takes off directly.

Apple's M-series chips are still consumer products. One year ago, they got rid of Intel, on the one hand to control product strength, on the other hand, it is to control costs and maximize profits. The erratic cost of a large-area SoC is clearly not what Apple expected.

▲ The highest unified memory of M1 Max is 64GB, then M1 Max Duo comes directly to 128GB?

On the other hand, if two or more M1 Max are spliced ​​together, the design of unified memory (UMA) will also be a huge problem. Re-plan the location of the multi-core, introduce larger bandwidth, and higher capacity memory. It is inevitable.

For the public, it may be a more complicated chip design, and for the private, it may invisibly increase the cost several times, which will be two major stumbling blocks for Apple's M chip to become more Max.

Moore's Law is in the past, the moment is now

"The number of transistors that can be accommodated on an integrated circuit will double about every two years." This is the famous Moore's Law, and it has another saying, "Every 18 months, the performance of the chip will double. "

▲ MacBook Pro 16. Picture from: dpreview

The performance here actually refers to the number of transistors. Compared with M1, M1 Max has a 3.5 times performance improvement, which just happens to reflect the difference in the number of transistors.

The number of transistors doubled in the M1 series, which is an increase in chip area. From a historical point of view, it is more dependent on technological progress, from μm to nm level, the number of transistors has also jumped from one million to one hundred million.

However, around 2013, Moore's Law has slowed down. From then to now, the performance benefits of the improvement of process nodes have been declining.

More advanced technology processes can indeed increase the number of transistors, but it is also accompanied by changes in cost and yield.

▲ TSMC is expected to start production of 3nm process in 2023. Picture from: anandtech

According to data released by the International Business Strategy Corporation (IBS), the design of a 3nm chip is expected to cost 590 million US dollars, while 5nm only costs 416 million US dollars, 7nm is 217 million US dollars, and 28nm is only 40 million US dollars.

TSMC has previously announced that it will invest 20 billion US dollars to build a 3nm wafer factory, also for 3nm, Samsung's cost is not lower than TSMC.

So far, only TSMC and Samsung are actively deploying 3nm wafers. Other manufacturers do not want to, but can't afford the money.

On the other hand, the yield rate of chips decreases as the area increases. The design pass rate of 700mm² is only about 30%. When it is reduced to 150mm², the yield rate soars to 80%.

No matter how you look at it, the road to chip upgrades seems to have been blocked.

▲ AMD EPYC 2 (Rome) processor based on Zen 2. Picture from: AMD

In order to continue to increase the chip scale and density, many people have turned their attention from the upgrade of the process node to the packaging process, which is AMD's Chiplet (small chip) technology.

In simple terms, Chiplet is like dumplings filled with glutinous rice balls, encapsulating small chips with different functions together, instead of cutting directly from the wafer, and using advanced packaging technology to make up for the stagnation of the process node.

▲ Currently the most vivid metaphor for Chiplet (but I don't approve of this way of eating).

In recent years, AMD has also used Chiplet technology to continuously increase processor density to counterattack Intel, and gradually began to grab the market.

For Chiplet, which has emerged in recent years, The Linley Group, an authoritative consulting organization in the technology industry, directly proposed that Chiplet can reduce the design cost of large 7nm chips by more than 25% in the article "Why Big Chips Are Getting Small". During the process, the cost savings will be even higher.

▲ AMD is based on the Ryzen 9 5900X CPU in a 3D Chiplet package.

And the 3D V-Cache announced by AMD is also confirming that Chiplet, which combines the old process and advanced packaging process, can achieve higher node performance, and even mix chips from different process nodes, with enough flexibility.

In addition to reducing costs and achieving more advanced performance, Chiplet will also speed up product launches. After all, it is enough to directly use old chips with advanced packaging processes, and even ignore the layout of advanced process nodes.

Having said so many advantages, Chiplet also has corresponding disadvantages. The stacking of small chips 2D and 3D has very high requirements for thermal management design, and the total thermal power consumption in the package will be significantly improved.

▲ Intel server chip based on Chiplet. Picture from: nextplatorm

But in any case, Chiplet has been recognized by many institutions and manufacturers as an important technology for continuous breakthroughs in chip performance in the post-Moore era.

▲ M1 inside the Mac mini and MacBook Air.

Going back to the original Apple self-developed M chip, through the ARM architecture and the upgrade of process nodes, the energy efficiency ratio is continuously improved, and the yield and cost are controlled by the way. As for whether it will combine multiple M1 Max together to form a complex giant SoC into a workstation-level Mac Pro, from the current point of view, Apple has enough capital and strength to design and produce a "prehistoric behemoth" processor.

▲ Unofficial rendering of iMac Pro 2022.

As for Chiplet, I think it must have appeared in the drawings of the Apple chip team. Instead of facing the future uncertain process node upgrade, it is better to actively seek changes and rely on the current M chip and A chip to combine to complete a deeper SoC. upgrade.

The M1 Max Duo that may appear is also very likely to become the largest SoC in the history of Apple's core manufacturing, and there will be no one to come.

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